`timescale 1ns/1ps
module edge_detection_top;
    reg reset,clock,A;
    wire B;

    always # 1 clock = ~clock;
    initial begin
        reset = 0;
        clock = 0;
        A = 0;
        # 2 reset =1;
        # 2 reset =0;
        # 4 A = 1;
        # 5 A = 0; 
        # 5 A = 1;
        # 5 A = 0;
        # 4 $stop;
    end
    edge_detection ed(B,reset,clock,A);
	initial
	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, ed);
 	end
endmodule

module edge_detection(B,reset,clock,A);
    input reset,clock,A;
    output B;
    reg Q1,Q2;
    assign B = Q1 ^ Q2; 
    always @(posedge clock or posedge reset)begin
        if (reset) begin
        	Q1 <= 0;
            Q2 <= 0;
        end
        else begin
        	Q1 <= A;
            Q2 <= Q1;
        end
    end

endmodule
